1. Field of the Invention
The invention relates to the field of semiconductor memory devices employing floating gates and the processes and methods for fabricating these devices.
2. Prior Art:
One class of non-volatile semiconductor memories employs floating gates, that is, gates which are completely surrounded by an insulative layer such as silicon dioxide. Typically, a polycrystalline silicon (polysilicon) layer is used to form floating gates. These gates are electrically charged, most often with electrons by transferring charge into and from the gates through a variety of mechanisms. The presence or absence of this charge represents stored, binary information. An early example of such a device is shown in U.S. Pat. No. 3,500,142.
A recent category of floating gate memory devices uses channel injection for charging floating gates and tunneling for removing charge from the gates. Here, each memory cell comprises only a single device and the entire memory array is erased at one time, that is, individual cells or groups of cells are not separately erasable as in current EEPROMs. These memories are sometimes referred to as "flash" EPROMs or "flash" EEPROMs.
U.S. Pat. No. 4,780,424 provides a process for fabricating a buried bit line device which avoids the increased capacitance of the prior an cells. This process includes fabricating contactless electrically programmable and electrically erasable memory cells. Elongated source and drain regions are formed, and then field oxide is grown on top of the source and drain regions. The drain regions are shallow compared to the source regions. Furthermore, the source regions have more graded junctions. The floating gates are formed over a tunnel oxide between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gate is formed simultaneously and in alignment with the word lines.
One problem with the fabrication of the flash contactless EPROMs or EEPROMs is that the processing is not compatible with self-aligned silicide technology. In the fabrication of other semiconductor devices, for example MOS transistors, this technology is used extensively. For example, during the fabrication of a MOS transistor, a refractory metal such as titanium can be deposited on the entire substrate surface. The substrate will next be put through a silicidation step, which will typically be accomplished by heating in an inert ambient or by rapid thermal annealing (RTA). The refractory metal will react with any exposed silicon or polysilicon to form a refractory metal silicide. The exposed silicon regions in the case of a MOS device where the silicide is formed are the same regions where the silicide is desired. Typically, this will be the gates and the source and drain regions. The refractory metal deposited on areas of the substrate which are not exposed silicon will either remain unreacted or will form a refractory metal nitride if the silicidation step is performed in a nitrogen ambient. A selective etch will then remove the unreacted refractory metal or refractory metal nitride while leaving the refractory metal silicide in place. Thus, the process forms a silicide on all regions where the silicide is desired, while removing all refractory metal from the other regions without a masking step. Since no masking step is needed, the process is self-aligned.
In the case of flash contactless EPROMs or EEPROMs, unlike the MOS transistor, there are regions of exposed silicon where no silicide is desired. These devices have elongated, parallel, alternating source and drain regions. Running perpendicular to these source and drain regions are elongated parallel polysilicon word lines. While it is desirable for the polysilicon word lines to be silicidized in order to lower their resistance, the regions bounded by the source and drain in one direction and the word lines in the other cannot be silicidized, as this would cause source to drain shorting. Unfortunately, these regions are exposed silicon at the stage of processing when the polysilicon word lines must be silicidized, so that self-aligned silicidation cannot be used in order to lower the resistance of the word line.
To overcome this problem, a blanket layer of silicon dioxide (SiO.sub.2) can be deposited, the exposed silicon regions where no silicide is desired can then be masked, and an etch performed to remove the SiO.sub.2 from all other regions of the substrate. Following this, the silicidation can be performed. However, this method is an unsatisfactory solution since it involves a deposition, masking and etch step in addition to the self-aligned silicide processing. Instead, the lowering of the resistance of the word lines is typically accomplished by first depositing a refractory metal silicide on the substrate surface. This is followed by a masking step and an etch step to leave the silicide on the word lines and nowhere else. Typically, tungsten silicide (WSi.sub.2) is used, even though it has a higher resistance than, e.g., titanium silicide (TiSi.sub.2). Titanium silicide is not used because, although it is desirable for its low resistance, it is much more difficult to etch than tungsten silicide. As an alternative to the deposition of a refractory metal followed by masking and etch, a heavily doped polysilicon can be used for the word lines. Although this method has the advantage of not requiring an additional masking and etch step, the resistance of heavily doped polysilicon is higher than any of the refractory metal silicides.
In addition to the processing advantages that self aligned silicidation offers, it is further desirous to use this technology during the contactless EPROM or flash EPROM manufacturing because it can be performed for the memory array simultaneously with the silicidation step of the peripheral circuits, thus further reducing processing steps.
What is needed is a process for fabricating flash array contactless EPROMs or EEPROMs which is compatible with self-aligned silicide technology. It is further desirable that any such process does not involve additional masking steps.